1. Field of the Invention
This invention relates generally to semiconductor metrology technology, and, more particularly, to various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10 is depicted in FIG. 1. The field effect transistor 10 may be formed above a surface 15 of a semiconducting substrate 12, such as a doped silicon wafer. The substrate 12 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped-polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16 that is formed above the surface 15 of the semiconducting substrate 12. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The sidewall spacer 20 may be formed above shallow source/drain extension regions 23. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 12. Shallow trench isolation regions 18 may be provided to electrically isolate the transistor 10 from neighboring semiconductor devices such as other transistors (not shown). The methodologies employed in forming such a transistor are well known to those skilled in the art.
When the transistor 10 is operational, i.e., when it is turned “ON” by applying the appropriate voltage to the gate electrode 14, a channel region 13, indicated by dashed lines, will be established in the substrate 12 between the source/drain regions 22. During operation, electrons will flow between the source/drain regions 22 in the channel region 17. The distance between the source/drain regions 22 is generally referred to as the “channel length” of the transistor 10, and it approximately corresponds to the length 12 of the gate electrode 14, i.e., the so-called critical dimension of the gate electrode 14. Channel length, at least in part, determines several performance characteristics of the transistor 10, such as switching speed.
FIG. 2 is a plan view of an illustrative semiconducting wafer 11 having a plurality of die 24 formed thereon. The die 24 represent areas of the wafer 11 wherein production integrated circuit devices, e.g., microprocessors, memory devices, bipolar devices, etc. may be formed. The number of die 24 per wafer may vary depending upon the particular application and the overall size of the wafer 11. For example, in connection with the fabrication of modern microprocessor devices, a typical 8-inch wafer has several hundred individual die positioned on the wafer 11. The area between the individual die is sometimes referred to as scribe lines 25. The relative size of the die 24 and the scribe lines 25 is exaggerated in FIG. 2 for purposes of clarity. Ultimately, after the fabrication of the production integrated circuit devices is complete, the wafer will be cut and the individual production devices will be tested, packaged and sold.
In manufacturing modern integrated circuit devices, various process operations are performed on the wafer 11 in a desired sequence so as to produce the integrated circuit device. Such process operations may include deposition processes, etching processes, annealing processes, planarization processes, and ion implantation processes. As indicated above, various implant regions are typically formed as a part of the process of manufacturing an integrated circuit device. Such implant regions are typically formed by performing one or more ion implantation processes and/or by performing one or more thermal diffusion processes. The ability to precisely control the characteristics of such doped regions, e.g., dopant species, concentration, implant profile, activation grade, etc., is critical in the formation of modern, high performance integrated circuit devices. In some cases, even slight variations in the characteristics of the doped regions versus the planned characteristics of such doped regions can adversely impact the performance capability of the resulting integrated circuit device.
Over the past several years, the gate length 12 of field effect transistors on modern high performance integrated circuit devices has been reduced to the level such that current generation transistor devices have a critical dimension on the order of approximately 40-70 nm, and further reductions are planned in the future. As the critical dimensions decrease, the depth and characteristics of the doped regions associated with such devices also tends to decrease. For example, using current technology, the source/drain regions 22 for such a transistor 10 may have a depth on the order of approximately 20-100 nm, whereas the extension regions 23 may have a depth on the order of approximately 10-20 nm. It is also important that the doped regions have the correct concentration of dopant material in order to function properly. Thus, the ability to control and determine the characteristics of doped regions in modern devices becomes ever more important. It should be understood that controlling the characteristics of the doped regions is equally important with other types of implants, e.g., halo implant regions, threshold voltage implant regions, etc. Doped regions that are also important in some modern semiconductor devices involve the formation of various doped wells, e.g., CMOS technology, bipolar transistors, etc.
As will be appreciated by those skilled in the art, various techniques are employed in an effort to insure that the doped regions are formed to their desired target characteristics, e.g., depth, dopant concentration, etc. In some cases, various ion implantation processes are performed on test wafers that are ultimately cross-sectioned and examined with a scanning electron microscope (SEM) or secondary ion mass spectrometry (SIMS) metrology tools to determine one or more characteristics of the doped regions. Such testing methodologies are expensive in that they involve at least partially processing the test wafers and, thereafter, performing the cross-sectioning and inspection activities to determine the characteristics of the doped regions. Moreover, such test wafers typically do not include any production devices. Additionally, in using such a testing methodology, there may be an unacceptable delay in receiving the results of such tests.
Efforts have been made to develop non-destructive methodologies for determining the characteristics of doped regions formed in manufacturing semiconductor devices. Typically, prior to performing an ion implantation process, a patterned layer of photoresist will be formed above the surface of the wafer. Thereafter, one or more ion implantation processes may be performed into the exposed silicon areas (as defined by the patterned masking layer) to form various doped regions therein. As indicated above, given the very small size of various features formed on a modern integrated circuit device, the size of such openings in the patterned layer of photoresist is very small, e.g., less than one micron. One vendor, Thermawave (of Fremont, Calif.), provides a metrology system wherein a laser is used in an effort to determine the characteristics of doped regions. The Thermawave instrument has pattern recognition capability that allows the device to locate the open areas within the patterned layer of photoresist such that the laser beam may be directed to the exposed silicon surface in an effort to determine the characteristics of the doped region. Unfortunately, in some applications, the Thermawave instrument lacks the required sensitivity to determine any meaningful information regarding the characteristics of the doped regions. For example, when the dopant concentration is relatively high, the Thermawave instrument provides little meaningful feedback due to its limited sensitivity. In these applications, if employed, the Thermawave-type instrument is used as a “GO/NO GO” check to determine if dopant material is present in the inspected region only. That is, due to its limited sensitivity, if such a device detects the presence of any dopant material, it is assumed that the correct amount of dopant material is present in the inspected region.
Another technique for determining the characteristics of doped regions involves performing a surface photovoltage charge metrology process to determine the characteristics of the doped regions. In accordance with this technique, a modulated beam of collimated light from a light source, e.g., blue or white light, is used to illuminate the desired area to be inspected. Based upon the measured surface photovoltage, characteristics of the doped region, e.g., dopant concentration, may be determined. However, the size of the light beam used in such metrology tools to illuminate the desired inspection target may be relatively large, e.g., approximately 1-2 mm. Unfortunately, with modern integrated circuit devices, the doped regions in need of inspection are much smaller than the size of the light beam used in traditional surface photovoltage metrology techniques.
Another non-destructive technique that is sometimes employed to determine one or more characteristics involves performing various electrical tests, e.g., resistivity, using a four-point probe. However, using such techniques involves waiting until an anneal process has been performed to activate the implanted dopant atoms. Due to a variety of reasons, there are limitations on when such an anneal process may be performed. Typically, such anneal processes are performed at the later stages of manufacturing. Thus, results from such electrical tests are not as timely as would otherwise be desired. Additionally, the physical size of the probes is relatively large and, therefore, such a testing methodology may be of limited use in connection with the testing of modern semiconductor devices which have very small doped regions. Moreover, such contact testing techniques may result in damage to the tested device.
When doped regions are formed in silicon-on-insulator substrates, traditional surface photovoltage measurement techniques are not very effective. FIG. 3 depicts an illustrative silicon-on-insulator substrate 100 comprised of a bulk layer 100A, a buried insulation layer 100B (a so-called “box” layer), and an active layer 100C. The active layer 100C has a surface 100S, and an interface 102 is present between the active layer 100C and the buried insulation layer 100B.
Traditional surface photovoltage metrology tools, like the one referenced above from QC Solutions, Inc., use light sources having relatively high energy levels, e.g., blue and white light sources. As stated above, dimensions of integrated circuit devices continue to shrink and, as a result, the depths of the doped regions become shallower and the profiles of the doped regions become steeper. Additionally, the depth 101 of the active layer 100C of an SOI structure also continues to decrease. For example, the depth 101 of the active layer 100C on SOI structures 100 employed in manufacturing current day integrated circuit devices may be approximately 800 nm, and further reductions are anticipated.
Unfortunately, the energy levels of light sources employed in existing surface photovoltage metrology tools is too high and the excited region goes beyond the interface 102 between the active layer 100C and the buried insulation layer 100B. Typically, the active layer 100C is comprised of silicon and the buried insulation layer 100B is comprised of silicon dioxide. The penetration of the excited region beyond the interface 102 causes such tools to be very insensitive as it relates to the measurement of one or more characteristics of various doped regions formed in the active layer 100C. This is believed to occur in at least some cases because oxygen tends to react to the silicon to form a dielectric capacitor. This may occur because the high energy light may generate electrons in the active zone below the transistor 10 and it is not possible to discharge this area due to the buried insulation layer 100B. As a result, a dielectric capacitor will be formed.
The present invention is directed to various methods and systems that may solve, or at least reduce the effects of, some or all of the aforementioned problems.